Hardware synthesis of weakly consistent C concurrency
File(s)NadeshFPGA17.pdf (620.38 KB)
Accepted version
Author(s)
Ramanathan, N
Fleming, S
Wickerson, J
Constantinides, GA
Type
Conference Paper
Abstract
Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via fine-grained atomic operations ('atomics'), have been shown empirically to be the fastest class of multi-threaded algorithms in the realm of conventional processors. This paper explores how these algorithms can be compiled from C to reconfigurable hardware via high-level synthesis (HLS). We focus on the scheduling problem, in which software instructions are assigned to hardware clock cycles. We first show that typical HLS scheduling constraints are insufficient to implement atomics, because they permit some instruction reorderings that, though sound in a single-threaded context, demonstrably cause erroneous results when synthesising multi-threaded programs. We then show that correct behaviour can be restored by imposing additional intra-thread constraints among the memory operations. We implement our approach in the open-source LegUp HLS framework, and provide both sequentially consistent (SC) and weakly consistent ('weak') atomics. Weak atomics necessitate fewer constraints than SC atomics, but suffice for many concurrent algorithms. We confirm, via automatic model-checking, that we correctly implement the semantics defined by the 2011 revision of the C standard. A case study on a circular buffer suggests that circuits synthesised from programs that use atomics can be 2.5x faster than those that use locks, and that weak atomics can yield a further 1.5x speedup.
Date Issued
2017-02-01
Date Acceptance
2016-11-20
Citation
FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate, 2017, pp.169-178
ISBN
9781450343541
Publisher
ACM
Start Page
169
End Page
178
Journal / Book Title
FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate
Copyright Statement
© 2017 ACM. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate, (Feb 2017) https://dl.acm.org/doi/10.1145/3020078.3021733
Sponsor
Royal Academy Of Engineering
Imagination Technologies Ltd
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Grant Number
Prof Constantinides Chair
Prof Constantinides Chair
11908 (EP/K034448/1)
EP/I020357/1
Source
ACM International Symposium on FPGAs 2017
Subjects
Science & Technology
Technology
Computer Science, Hardware & Architecture
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
Computer Science
Engineering
atomic operations
C/C plus
FPGAs
high-level synthesis
lock-free algorithms
memory consistency models
scheduling
Publication Status
Published
Start Date
2017-02-22
Finish Date
2017-02-24
Coverage Spatial
Monterey, CA