AMPLE: Event-driven accelerator for mixed-precision inference of graph neural networks
File(s) 3721146.3721963.pdf (816.46 KB)
Published version
Author(s)
Gimenes, Pedro
Zhao, Aaron
Constantinides, George A
Type
Conference Paper
Abstract
Graph Neural Networks (GNNs) have recently gained attention due to their performance on non-Euclidean data. The use of custom hardware architectures proves particularly beneficial for GNNs due to their irregular memory access patterns, resulting from the sparse structure of graphs. However, existing FPGA accelerators are limited by their double buffering mechanism, which doesn't account for the irregular node distribution in typical graph datasets. To address this, we introduce AMPLE (Accelerated Message Passing Logic Engine), an FPGA accelerator leveraging a new event-driven programming flow. We develop a mixed-arithmetic architecture, enabling GNN inference to be quantized at a node-level granularity. Finally, prefetcher for data and instructions is implemented to optimize off-chip memory access and maximize node parallelism. Evaluation on citation and social media graph datasets ranging from 2K to 700K nodes showed a mean speedup of 243× and 7.2× against CPU and GPU counterparts, respectively.
Date Issued
2025-03-01
Date Acceptance
2025-03-01
Citation
EuroMLSys '25: Proceedings of the 5th Workshop on Machine Learning and Systems, 2025, pp.107-113
ISBN
9798400715389
Publisher
ACM
Start Page
107
End Page
113
Journal / Book Title
EuroMLSys '25: Proceedings of the 5th Workshop on Machine Learning and Systems
Copyright Statement
© 2025 Copyright held by the owner/author(s). This work is licensed under Creative Commons Attribution International 4.0.
License URL
Identifier
10.1145/3721146.3721963
Source
EuroMLSys '25: 5th Workshop on Machine Learning and Systems
Subjects
CCS Concepts: • Hardware → Hardware accelerators; Reconfigurable logic applications FPGA
Graph Neural Networks
Graph Convolutional Networks
Neural Network Quantization
Mixed-Precision Neural Networks
Graph Processing
Network-on-Chip
Hardware Architecture
Publication Status
Published
Start Date
2025-03-30
Finish Date
2025-04-03
Coverage Spatial
Rotterdam, Netherlands
Date Publish Online
2025-04-01
