The growing need to obtain large amounts of genomic data for various applications has motivated efforts to drop the cost and time of DNA sequencing and assembly. At the forefront of these, semiconductor based sequencing using Ion-Sensitive Field Effect Transistors (ISFETs) shows great promise. This thesis explores methods to improve ISFET sensor performance using novel front-end topologies in CMOS in addition to introducing new real-time parallel processing methods to allow more robust and rapid DNA sequencing and assembly in hardware.

The novel front-ends utilise capacitive feedback.
By doing so, all the existing challenges in ISFET sensors such as trapped charge, sensitivity loss and drift can be solved. Three different topologies ( two-stage, single-stage and 3-Transistor) are discussed and compared. The single stage front-end is also found to be the most suitable structure for implementing large arrays of sensors.

A novel automatic calibration system is designed to compensate for the gain mismatches in the sensor array, which monitors the amplitude of high frequency sine waves superimposed on the chemical signals. A trade-off between speed and resolution is resolved by adding additional lowpass filters in the loop.

Following this, a full system comprising a $32\times32$ ISFET array, an automatic gain calibration system, control logics and SPI is implemented. The correlated double sampling system which eliminates the offset problem is realized in digital domain. An SPI protocol is used to send off the digitalised data to off-chip memory, as well as the data retrieval. The test results indicate a good performance in offset cancellation and gain consistency.

Finally a real-time DNA fragment comparison system is implemented in the FPGA for DNA assembly. To handle with the incomplete data set during the sequencing time, a novel hybrid comparison algorithm is proposed. The original all-against-all comparison step in the OLC method is firstly decomposed into successive window-against-window comparison phases, and then dynamic programming is grafted on the exact comparison to achieve high speed but error-tolerant computation. Hierarchical implementation in FPGA is represented where processing units are paralleled and controlled by one global controller. The validation of the proposed system is proven by the assembly of three real DNA sets even with deliberate errors introduced.