Customizable FPGA-based accelerator for binarized graph neural networks
File(s)
Accepted version
Author(s)
Wang, Ziwei
Que, Zhiqiang
Luk, Wayne
Fan, Hongxiang
Type
Conference Paper
Abstract
Graph convolutional networks (GCNs) have demonstrated their excellent algorithmic performance in various graph-based learning applications. Nevertheless, the massive amount of computation required by analyzing graph data structures puts a heavy burden on the hardware performance, limiting their deployment in real-life scienarios. To address this issue, we propose a customizable FPGA-based design to accelerate binarized GCNs (BiGCNs). The proposed accelerator is parameterized by different loop unrolling and memory partition factors, which can be reconfigured to fulfill different user needs. To ease the bandwidth requirement of BiGCNs, our design overlaps the data transfer with computation. We also adopt COO
(Coordinate) format storage for the adjacency matrix to skip the redundant computation to improve hardware performance. Our experimental results demonstrate that the proposed FPGA-based BiGCN design achieves 202× and 10.6× speedup than CPU and GPU implementations on the Flickr dataset.
(Coordinate) format storage for the adjacency matrix to skip the redundant computation to improve hardware performance. Our experimental results demonstrate that the proposed FPGA-based BiGCN design achieves 202× and 10.6× speedup than CPU and GPU implementations on the Flickr dataset.
Date Issued
2022-11-11
Date Acceptance
2022-01-15
Citation
2022, pp.1968-1972
Publisher
IEEE
Start Page
1968
End Page
1972
Copyright Statement
Copyright © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Identifier
https://ieeexplore.ieee.org/abstract/document/9937817
Source
International Symposium on Circuits and Systems (ICAS 2022)
Publication Status
Published
Start Date
2022-05-28
Finish Date
2022-06-01
Coverage Spatial
Austin, Texas, USA
Date Publish Online
2022-11-11