FPGAs are being increasingly used on networkinterface cards (NICs) as offload units to accelerate packetprocessing tasks. The rationale is that by customizing the NIClogic it is possible to achieve higher performance for the mostcritical tasks while eliminating unnecessary logic, thus improvingoverall efficiency.In this paper, we aim to investigate if similar benefits canalso be extended to network switches. We compare differentswitch architectures and analyze their suitability to an FPGAimplementation. We discuss several optimization techniques toovercome the challenges of limited FPGA resources and assessthe scalability of our designs up to 10, 25, and 50 Gb/s throughputper port.