Modulo scheduling with rational initiation intervals in custom hardware design
Author(s)
Sittel, Patrick
Wickerson, John
Kumm, Martin
Zipf, Peter
Type
Conference Paper
Abstract
In modulo scheduling, the number of clock cycles between successive inputs (theinitiation interval, II) is tradi-tionally aninteger, but in this paper, we explore the benefitsof allowing it to be a rational number. This rational II canbe interpreted as theaveragenumber of clock cycles betweensuccessive inputs. As the minimum rational II can be less thanthe minimum integer II, this translates to higher throughput. We formulate rational-II modulo scheduling as an integer linear programming (ILP) problem that is able to find latency-optimal schedules for a fixed rational II. We have applied our scheduler to a standard benchmark of hardware designs, and our resultsdemonstrate a significant speedup compared to state-of-the-artinteger-II and rational-II formulations.
Date Issued
2020-03-26
Date Acceptance
2019-09-03
Citation
2020, pp.1-6
Publisher
IEEE
Start Page
1
End Page
6
Copyright Statement
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (E
Identifier
https://ieeexplore.ieee.org/abstract/document/9045616
Grant Number
Ref: 542716
Source
Asia South Pacific Design Automation Conference (ASP-DAC)
Publication Status
Published
Start Date
2020-01-13
Finish Date
2020-01-16
Coverage Spatial
Beijing
Date Publish Online
2020-03-26