POLSCA: Polyhedral high-level synthesis with compiler transformations
File(s) POLSCA_FPL_2022.pdf (281.62 KB)
Accepted version
Author(s)
Zhao, Ruizhe
Cheng, Jianyi
Luk, Wayne
Constantinides, George A
Type
Conference Paper
Abstract
Polyhedral optimization can parallelize nested affine
loops for high-level synthesis (HLS), but polyhedral tools are
HLS-agnostic and can worsen performance. Moreover, HLS tools
require user directives which can produce unreadable polyhedral-
transformed code. To address these two challenges, we present
POLSCA, a compiler framework that improves polyhedral HLS
workflow by automatic code transformation. POLSCA decom-
poses a design before polyhedral optimization to balance code
complexity and parallelism, while revising memory interfaces
of polyhedral-transformed code to make partitioning explicit
for HLS tools; it enables designs to benefit more easily from
polyhedral optimization. Experiments on Polybench/C show that
POLSCA designs are 1.5 times faster on average compared with
baseline designs generated directly from applying HLS on C code.
loops for high-level synthesis (HLS), but polyhedral tools are
HLS-agnostic and can worsen performance. Moreover, HLS tools
require user directives which can produce unreadable polyhedral-
transformed code. To address these two challenges, we present
POLSCA, a compiler framework that improves polyhedral HLS
workflow by automatic code transformation. POLSCA decom-
poses a design before polyhedral optimization to balance code
complexity and parallelism, while revising memory interfaces
of polyhedral-transformed code to make partitioning explicit
for HLS tools; it enables designs to benefit more easily from
polyhedral optimization. Experiments on Polybench/C show that
POLSCA designs are 1.5 times faster on average compared with
baseline designs generated directly from applying HLS on C code.
Date Issued
2023-02-13
Date Acceptance
2022-06-20
Citation
2023, pp.235-242
Publisher
ACM
Start Page
235
End Page
242
Copyright Statement
Copyright © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Identifier
https://ieeexplore.ieee.org/abstract/document/10035220
Source
32nd International Conference on Field Programmable Logic and Applications
Publication Status
Published
Start Date
2022-08-29
Finish Date
2022-09-02
Coverage Spatial
Belfast, Northern Ireland
Date Publish Online
2023-02-13
