A case for precise, fine-grained pointer synthesis in high-level synthesis
File(s)TODAES_21.pdf (610.92 KB)
Accepted version
Author(s)
Ramanathan, Nadesh
Constantinides, George
Wickerson, John
Type
Journal Article
Abstract
This article combines two practical approaches to improve pointer synthesis within HLS tools. Both approaches
focus on inefficiencies in how HLS tools treat the points-to graph – a mapping that connects each instruction to
the memory locations that it might access at runtime. HLS pointer synthesis first compute the points-to graph
via pointer analysis and then implements its connections in hardware, which gives rise to two inefficiencies.
Firstly, HLS tools typically favour pointer analysis that is fast, sacrificing precision. Secondly, they also favour
centralising memory connections in hardware for instructions that can point to more than one location.
In this article, we demonstrate that a more precise pointer analysis coupled with decentralised memory
connections in hardware can substantially reduce the unnecessary sharing of memory resources. We implement
both flow- and context-sensitive pointer analysis and fine-grained memory connections in two modern HLS
tools, LegUp and Vitis HLS. An evaluation on three benchmark suites, ranging from non-trivial pointer use
to standard HLS benchmarks, indicates that when we improve both precision and granularity of pointer
synthesis, on average, we can reduce area and latency by around 42% and 37% respectively.
focus on inefficiencies in how HLS tools treat the points-to graph – a mapping that connects each instruction to
the memory locations that it might access at runtime. HLS pointer synthesis first compute the points-to graph
via pointer analysis and then implements its connections in hardware, which gives rise to two inefficiencies.
Firstly, HLS tools typically favour pointer analysis that is fast, sacrificing precision. Secondly, they also favour
centralising memory connections in hardware for instructions that can point to more than one location.
In this article, we demonstrate that a more precise pointer analysis coupled with decentralised memory
connections in hardware can substantially reduce the unnecessary sharing of memory resources. We implement
both flow- and context-sensitive pointer analysis and fine-grained memory connections in two modern HLS
tools, LegUp and Vitis HLS. An evaluation on three benchmark suites, ranging from non-trivial pointer use
to standard HLS benchmarks, indicates that when we improve both precision and granularity of pointer
synthesis, on average, we can reduce area and latency by around 42% and 37% respectively.
Date Issued
2022-03-08
Date Acceptance
2021-10-13
Citation
ACM Transactions on Design Automation of Electronic Systems, 2022, 27 (4), pp.1-26
ISSN
1084-4309
Publisher
Association for Computing Machinery (ACM)
Start Page
1
End Page
26
Journal / Book Title
ACM Transactions on Design Automation of Electronic Systems
Volume
27
Issue
4
Copyright Statement
© 2022 Association for Computing Machinery. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM Transactions on Design Automation of Electronic SystemsVolume 27 Issue 4 July 2022 Article No: 30pp 1–26 https://doi.org/10.1145/3491430
Sponsor
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Grant Number
EP/P010040/1
Ref: 542716
Subjects
Design Practice & Management
0803 Computer Software
1006 Computer Hardware
Publication Status
Published
Article Number
ARTN 30