Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions
File(s)
Working paper
Author(s)
Papaphilippou, Philippos
Kelly, Paul HJ
Luk, Wayne
Type
Working Paper
Abstract
This paper presents a novel, non-standard set of vector instruction types for exploring custom SIMD instructions in a softcore. The new types allow simultaneous access to a relatively high number of operands, reducing the instruction count where applicable. Additionally, a high-performance open-source RISC-V (RV32 IM) softcore is introduced, optimised for exploring custom SIMD instructions and streaming performance. By providing instruction templates for instruction development in HDL/Verilog, efficient FPGA-based instructions can be developed with few low-level lines of code. In order to improve custom SIMD instruction performance, the softcore's cache hierarchy is optimised for bandwidth, such as with very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications on an FPGA. Although the exploration is based on the softcore, the goal is to provide a means to experiment with advanced SIMD instructions which could be loaded in future CPUs that feature reconfigurable regions as custom instructions. Finally, we provide some insights on the challenges and effectiveness of such future micro-architectures.
Date Issued
2021-06-17
Citation
2021
Copyright Statement
© 2021 The Author(s)
Sponsor
Dunnhumby Limited
Engineering & Physical Science Research Council (EPSRC)
Identifier
http://philippos.info/papers/
Grant Number
PO: 250130012887
EP/P010040/1
Subjects
FPGAs
RISC-V
softcore
SIMD
cache hierarchy
reconfigurable
custom instructions
big data
streaming
sorting
prefix scan
Notes
Accepted at the Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), co-located with ISCA 2021
Publication Status
Accepted