Causal discovery is a technique to find the causal relationship be-
tween variables using data. This technique has many applications
in data mining and knowledge discovery. However, the high data di-
mensionality results in a significant computational efficiency prob-
lem. A common speed bottleneck in conventional causal discovery
methods is the execution of conditional independence (CI) tests.
This paper proposes, analyzes, and evaluates a novel acceleration
strategy for causal discovery, which has low communication costs
and can effectively exploit FPGA on-chip memory and parallelism.
First, we propose an algorithmic method to shift the speed bottle-
neck from CI test execution to CI test generation. Second, we design
a hardware accelerator for CI test generation on FPGAs. Third, we
evaluate the proposed approach by comparing the accuracy-speed
trade-off against four state-of-the-art accelerated causal discovery
tools on CPUs and GPUs. Our accelerated implementation running
on an Intel Arria 10 GX FPGA shows a superior accuracy-speed
trade-off in 12 causal discovery problems. The implementation
achieves up to 8.8 times speedup over the cuPC software running
on an NVIDIA GeForce RTX 2080 Ti GPU. It also achieves up to
155.7 times speedup over the stable.fast software running on an
Intel Xeon Silver 4110 octa-core CPU. To the best of our knowl-
edge, the proposed approach is the first FPGA-based acceleration
approach for constraint-based causal discovery.