Exploiting the correlation between dependence distance and latency in loop pipelining for HLS
File(s)
Accepted version
Author(s)
Cheng, Jianyi
Wickerson, John
Constantinides, George
Type
Conference Paper
Abstract
High-level synthesis (HLS) automatically transforms high-level programs in a language such as C/C++ into a low-level hardware description. In this context, loop pipelining is a key optimisation method for improving hardware performance. The main performance bottleneck of a pipelined loop is the ratio between two values: the latency of each iteration and the dependence distance of the operations in the loop. These two values are usually not known exactly, so existing HLS schedulers model them independently, which can cause sub-optimal performance. This paper extends state-of-the-art static schedulers with a fully automated pass that exposes and takes advantage of potential correlation between these two values, enabling smaller initiation intervals (II). We use the Microsoft Boogie software verifier to prove the existence of these correlations, which allows HLS tools to automatically find a high-performance hardware solution while maintaining correctness. Our results show that for a certain class of programs, our approach achieves, on average, an 11.1×performance gain at the cost of a 95% area overhead.
Date Issued
2021-10-12
Date Acceptance
2021-05-14
Citation
2021, pp.341-346
Publisher
IEEE
Start Page
341
End Page
346
Copyright Statement
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (EPSRC)
Identifier
https://ieeexplore.ieee.org/abstract/document/9556337
Grant Number
EP/P010040/1
Source
Field-Programmable Logic and Applications
Subjects
Science & Technology
Technology
Computer Science, Hardware & Architecture
Computer Science, Software Engineering
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
Computer Science
Engineering
High-Level Synthesis
Loop Pipelining
Formal Methods
Publication Status
Published
Start Date
2021-08-30
Finish Date
2021-09-03
Coverage Spatial
Virtual
Date Publish Online
2021-10-12