Despite its many flaws, Verilog is today both the most
popular hardware design language and a popular language for
communication between hardware development tools. Ever since
the language was standardised, researchers have made attempts
at formalising its semantics. To this day, no such attempt has
been fully successful. In this paper, we highlight one – we think,
important – concurrency problem in Verilog’s semantics that
has, for now, sidetracked our own ongoing Verilog semantics
formalisation attempt. To us, the problem calls for a clarification
of the Verilog standard. We propose a potential fix for the problem.