This thesis investigates the potential of network switches based on FPGA (field-programmable gate array) technology for high-performance applications. There are three contributions. The first contribution quantifies the gap between current ASIC-based (application-specific integrated circuit) switches and FPGA-based switches. We propose a novel buffer-sharing design to make efficient use of the FPGA on-chip memory. We also develop techniques for predicting the performance and resource requirements of the proposed switch design. The second contribution is a novel architecture for random projection and ensemble learning that targets an FPGA-based switch, utilising spare computational resources on the FPGA. This design is capable of processing high-dimensional data effectively for training ensemble models. We also create a model for efficient load distribution between the switch and the downstream servers. The proposed architecture enables a reduction in ensemble training time while maintaining high accuracy, with up to 6.7 times speed-up. The third contribution explores the benefit of kNN (k nearest neighbour) classification using the Hamming distance metric. We introduce a new architecture that enables complete application offloading to an FPGA-based switch. Our results show an estimated speed-up of up to 8.7 times and a memory reduction of up to 27.7 times.