Using SMT to accelerate nested virtualization
File(s)isca19_svt - public.pdf (889.74 KB)
Accepted version
Author(s)
Vilanova, Lluís
Amit, Nadav
Etsion, Yoav
Type
Conference Paper
Abstract
IaaS datacenters offer virtual machines (VMs) to their clients, who in turn sometimes deploy their own virtualized environments, thereby running a VM inside a VM. This is known as nested virtualization.
VMs are intrinsically slower than bare-metal execution, as they often trap into their hypervisor to perform tasks like operating virtual I/O devices. Each VM trap requires loading and storing dozens of registers to switch between the VM and hypervisor contexts, thereby incurring costly runtime overheads. Nested virtualization further magnifies these overheads, as every VM trap in a traditional virtualized environment triggers at least twice as many traps.
We propose to leverage the replicated thread execution resources in simultaneous multithreaded (SMT) cores to alleviate the overheads of VM traps in nested virtualization. Our proposed architecture introduces a simple mechanism to colocate different VMs and hypervisors on separate hardware threads of a core, and replaces the costly context switches of VM traps with simple thread stall and resume events. More concretely, as each thread in an SMT core has its own register set, trapping between VMs and hypervisors does not involve costly context switches, but simply requires the core to fetch instructions from a different hardware thread. Furthermore, our inter-thread communication mechanism allows a hypervisor to directly access and manipulate the registers of its subordinate VMs, given that they both share the same in-core physical register file.
A model of our architecture shows up to 2.3× and 2.6× better I/O latency and bandwidth, respectively. We also show a software-only prototype of the system using existing SMT architectures, with up to 1.3× and 1.5× better I/O latency and bandwidth, respectively, and 1.2--2.2× speedups on various real-world applications.
VMs are intrinsically slower than bare-metal execution, as they often trap into their hypervisor to perform tasks like operating virtual I/O devices. Each VM trap requires loading and storing dozens of registers to switch between the VM and hypervisor contexts, thereby incurring costly runtime overheads. Nested virtualization further magnifies these overheads, as every VM trap in a traditional virtualized environment triggers at least twice as many traps.
We propose to leverage the replicated thread execution resources in simultaneous multithreaded (SMT) cores to alleviate the overheads of VM traps in nested virtualization. Our proposed architecture introduces a simple mechanism to colocate different VMs and hypervisors on separate hardware threads of a core, and replaces the costly context switches of VM traps with simple thread stall and resume events. More concretely, as each thread in an SMT core has its own register set, trapping between VMs and hypervisors does not involve costly context switches, but simply requires the core to fetch instructions from a different hardware thread. Furthermore, our inter-thread communication mechanism allows a hypervisor to directly access and manipulate the registers of its subordinate VMs, given that they both share the same in-core physical register file.
A model of our architecture shows up to 2.3× and 2.6× better I/O latency and bandwidth, respectively. We also show a software-only prototype of the system using existing SMT architectures, with up to 1.3× and 1.5× better I/O latency and bandwidth, respectively, and 1.2--2.2× speedups on various real-world applications.
Date Issued
2019-06-22
Date Acceptance
2019-03-15
Citation
ISCA '19: Proceedings of the 46th International Symposium on Computer Architecture, 2019, pp.750-761
ISBN
9781450366694
Start Page
750
End Page
761
Journal / Book Title
ISCA '19: Proceedings of the 46th International Symposium on Computer Architecture
Copyright Statement
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.
This is the author’s version of the work. It is posted here for your personal use. Not
for redistribution. The definitive Version of Record was published in The 46th Annual
International Symposium on Computer Architecture (ISCA ’19), June 22–26, 2019, Phoenix,
AZ, USA, https://doi.org/10.1145/3307650.3322261.
This is the author’s version of the work. It is posted here for your personal use. Not
for redistribution. The definitive Version of Record was published in The 46th Annual
International Symposium on Computer Architecture (ISCA ’19), June 22–26, 2019, Phoenix,
AZ, USA, https://doi.org/10.1145/3307650.3322261.
Identifier
https://dl.acm.org/doi/10.1145/3307650.3322261
Source
International Symposium on Computer Architecture (ISCA)
Subjects
Science & Technology
Technology
Computer Science, Hardware & Architecture
Computer Science
virtualization
nested virtualization
computer architecture
Publication Status
Published
Start Date
2019-06-22
Finish Date
2019-06-26
Coverage Spatial
Phoenix, Arizona, USA
Date Publish Online
2019-06-22