This paper presents an ultra-low power SoC for automatic sle
ep staging using a single electroen-
cephalography (EEG) channel. The system integrates an anal
og front-end for EEG data acquisition and a
digital processor to extract spectral features from this da
ta and classify them into one of the sleep stages.
The digital processor consists of multiple blocks implemen
ting an automatic sleep staging algorithm
that uses a set of contextual decision trees controlled by a s
tate machine. The processor is designed
to stay in idle mode at most times waking up only when computat
ions are required. In addition, the
mathematical operations are implemented in a way such that t
he number of datapath components needed
is very small. The SoC is implemented in AMS 0.18
μ
m CMOS technology and is powered using a
single 1.25V supply. Its power consumption is measured to be
575
μ
W while its classification accuracy
using real EEG data is 98.7%.