High-level Synthesis (HLS) tools have greatly in-creased the productivity of FPGA application development,making it possible to easily create highly-parallel application-accelerators. However, while FPGAs are known for the ability tocustomise the number representation of data-paths, most HLSwork only uses custom-precision for fixed-point representations,and for floating-point relies on the 64-, 32-, and 16-bit for-mats provided by vendors. This paper presents a solution forparametrised floating-point in HLS via C++ templates, allowingfor compile-time selection of exponent and fraction widths,including the use of mixed precisions for input arguments andresult types. By using arbitrary width integers and compile-time logic the resulting operators describe the same data-pathas an external floating-point IP generator, while still allowingthe HLS tool to perform detailed optimisation and scheduling ofthe internal components. We show that the resulting custom-width HLS cores provide similar area and performance toplatform-native vendor IP blocks, while adding full support forheterogeneous precision floating-point data-paths to HLS tools.