A Survey of the implementation of linear model predictive control on FPGAs
File(s)
Accepted version
Author(s)
McInerney, Ian
Constantinides, George
Kerrigan, EC
Type
Conference Paper
Abstract
Over the past 20 years, great strides have been made in the real-time implementation
of linear MPC on FPGA devices. Starting from initial work, which demonstrated the benefits of
embedding linear MPC onto FPGAs, recent work has shown sampling rates of more than 1 MHz
are possible with FPGA-based implementations. This work surveys FPGA implementations
of linear MPC, with a focus on the computational architecture. This includes the choice of
number representation, the parallelizations exploited and the memory architecture. We discuss
the transferability of those design choices to the FPGA implementation of nonlinear MPC, and
provide some future research directions related to the implementation of MPC on FPGAs.
of linear MPC on FPGA devices. Starting from initial work, which demonstrated the benefits of
embedding linear MPC onto FPGAs, recent work has shown sampling rates of more than 1 MHz
are possible with FPGA-based implementations. This work surveys FPGA implementations
of linear MPC, with a focus on the computational architecture. This includes the choice of
number representation, the parallelizations exploited and the memory architecture. We discuss
the transferability of those design choices to the FPGA implementation of nonlinear MPC, and
provide some future research directions related to the implementation of MPC on FPGAs.
Date Issued
2018-08-22
Date Acceptance
2018-06-08
Citation
IFAC-PapersOnLine, 2018, pp.381-387
ISSN
2405-8963
Publisher
IFAC Secretariat
Start Page
381
End Page
387
Journal / Book Title
IFAC-PapersOnLine
Copyright Statement
© 2018, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.
Identifier
https://www.sciencedirect.com/science/article/pii/S2405896318327216?via%3Dihub
Source
6th IFAC Conference on Nonlinear Model Predictive Control
Subjects
linear MPC
embedded optimization
Field Programmable Gate Array (FPGA)
OPTIMIZATION
Publication Status
Published online
Start Date
2018-08-19
Finish Date
2018-08-22
Coverage Spatial
Madison, Wisconsin (USA)
Date Publish Online
2018-11-22