During the design of complex systems, designers need to know how their algorithm
or hardware is going to perform early in the design process. Tools exist to predict
performance metrics based on low-level parameters which are difficult to extract and are
dependent on specific implementation or architecture details which are only available
in the later stages of design. There needs to exist a model that is able to predict
performance metrics based on the algorithm being executed and the architecture it is
being executed on while using easily extractable parameters available early in design.
This thesis introduces a framework for designers that assists them in the early stages
of design. By having early estimations of performance based on the underlying hardware,
greater savings can be achieved when compared to other methods which can only occur
late in the design stage. Soft processors are used in the construction of the predictive
models as they are flexible and allow for complex models to be created that explore the
relationship between algorithm and hardware parameters.
First, an accurate model for performance estimation is developed that uses both
algorithm and architecture parameters. The method for extracting meaningful parameters
of algorithms without the need for implementation is described and forms an important
basis for this work. In predicting FPGA core power and off-chip device power, the
model performs well with mean errors under 2%, while the error is slightly higher when
predicting execution time.
Next, a framework is proposed that uses this accurate model to analyze the performance
of the algorithm in question to give the designer useful guidance not present in existing
state-of-the-art approaches. The framework allows the user to see the interaction between
the algorithm and the underlying hardware. This allows for early design space exploration
that can produce more efficient hardware. Sensitivity analysis is performed in order to
assess the performance of the proposed framework under noisy input parameters that
model user uncertainty. Further, the properties of the modeling technique are used to
provide the user with a measure of prediction confidence. Finally, the framework’s ability
to predict the effect of single event upsets in the arithmetic hardware is examined. This
is done by creating additional predictive models to examine the execution time cost in
the event of faulty multipliers or dividers.