ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development.
File(s)fpga18hcn.pdf (2.6 MB)
Accepted version
Author(s)
Ng, H-C
Liu, S
Luk, W
Type
Conference Paper
Abstract
This paper introduces ADAM, an approach for merging multiple FPGA designs into a single hardware design, so that multiple place-and-route tasks can be replaced by a single task to speed up functional evaluation of designs, especially during the development process. ADAM has three key elements. First, a novel approximate maximum common subgraph detection algorithm with linear time complexity to maximize sharing of resources in the merged design. Second, a prototype tool implementing this common subgraph detection algorithm for dataflow graphs derived from Verilog designs; this tool would also generate the appropriate control circuits to enable selection of the original designs at runtime. Third, a comprehensive analysis of compilation time versus degree of similarity to identify the optimized user parameters for the proposed approach. Experimental results show that ADAM can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case of binomial filters.
Editor(s)
Anderson, JH
Bazargan, K
Date Issued
2018-02-15
Online Publication Date
2018-02-15
2018-08-09T15:54:25Z
Date Acceptance
2018-02-01
Publisher
ACM
Start Page
189
End Page
198
Journal / Book Title
FPGA'18 Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Copyright Statement
©
2018 Association for Computing Machinery.
2018 Association for Computing Machinery.
Source Database
dblp
Sponsor
Commission of the European Communities
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Identifier
http://doi.acm.org/10.1145/3174243
Grant Number
671653
516075101 (EP/N031768/1)
EP/P010040/1
Source
FPGAInternational Symposium on Field Programmable Gate Arrays
Date Publish Online
2018-02-15