Modern multicore and manycore processors exhibit multiple levels of parallelism
through a wide range of architectural features such as SIMD for data parallel
execution or threads for core parallelism. The exploitation of multi-level parallelism
is therefore crucial for achieving superior performance on current and
future processors. This paper presents the performance tuning of a multiblock
CFD solver on Intel SandyBridge and Haswell multicore CPUs and the Intel
Xeon Phi Knights Corner coprocessor. Code optimisations have been applied
on two computational kernels exhibiting different computational patterns: the
update of flow variables and the evaluation of the Roe numerical fluxes. We
discuss at great length the code transformations required for achieving effi-
cient SIMD computations for both kernels across the selected devices including
SIMD shuffles and transpositions for flux stencil computations and global memory
transformations. Core parallelism is expressed through threading based
on a number of domain decomposition techniques together with optimisations
pertaining to alleviating NUMA effects found in multi-socket compute nodes.
Results are correlated with the Roofline performance model in order to assert
their efficiency for each distinct architecture. We report significant speedups
for single thread execution across both kernels: 2-5X on the multicore CPUs
and 14-23X on the Xeon Phi coprocessor. Computations at full node and chip
concurrency deliver a factor of three speedup on the multicore processors and
up to 24X on the Xeon Phi manycore coprocessor.