EURECA architectures have been proposed as an
enhancement to the existing FPGAs, to enable cycle-by-cycle
reconfiguration. Applications with irregular data accesses, which
previously cannot be efficiently supported in hardware, can
be efficiently mapped into EURECA architectures. One major
challenge to apply the EURECA architectures to practical
applications is the intensive design efforts required to analyse
and optimise cycle-reconfigurable operations, in order to obtain
accurate and high-performance results while underlying circuits
reconfigure cycle by cycle. In this work, we propose compiler
support for EURECA-based designs. The compiler support
adopts techniques based on session types to automatically derive a
runtime reconfiguration scheduler that guarantees design correct-
ness; and a streaming circuit model to ensure high-performance
circuits. Three benchmark applications —large-scale sorting,
Memcached, and SpMV— developed with the proposed compiler
support show up to 11.2 times (21.8 times when architecture
scales) reduction in area-delay product when compared with
conventional architectures, and achieve up to
39%
improvements
compared with manually optimised EURECA designs.