An improved data-driven memristor model accounting for sequences stimulus features
File(s)
Accepted version
Author(s)
Type
Conference Paper
Abstract
The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.
Date Acceptance
2023-02-15
Citation
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
ISBN
978-1-6654-5109-3
ISSN
2158-1525
Publisher
IEEE
Journal / Book Title
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Copyright Statement
Copyright © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Identifier
https://ieeexplore.ieee.org/document/10182200
Source
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Publication Status
Published
Start Date
2023-05-21
Finish Date
2023-05-25
Coverage Spatial
Monterey California , USA
Date Publish Online
2023-07-21