A SoC for an active implantable microsystem for closed-loop optogenetic neuromodulation
Author(s)
Type
Conference Paper
Abstract
This paper presents a system-on-chip (SoC) architecture for an active implantable microsystem that combines
electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000 Hz bandwidth, 10 mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2 mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has
an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180 nm CMOS process, with each chip occupying a 5 mm×2.45 mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.
electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000 Hz bandwidth, 10 mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2 mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has
an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180 nm CMOS process, with each chip occupying a 5 mm×2.45 mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.
Date Issued
2025-06-27
Date Acceptance
2025-01-20
Citation
2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp.1-5
Publisher
IEEE
Start Page
1
End Page
5
Journal / Book Title
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
Copyright Statement
Copyright © 2025, IEEE. This is the author’s accepted manuscript made available under a CC-BY licence in accordance with Imperial’s Research Publications Open Access policy (www.imperial.ac.uk/oa-policy)
License URL
Source
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
Publication Status
Published
Start Date
2025-05-26
Finish Date
2025-05-28
Coverage Spatial
London, United Kingdom