Graphical modelling of pinched hysteresis loops of memristors
File(s)IET-SMT.2016.0210.pdf (2.67 MB)
Accepted version
Author(s)
Wang, XM
Hui, SYR
Type
Journal Article
Abstract
In this study, a graphical modelling approach of the pinched hysteresis loops exhibited by memristors is presented. This method provides a tool to emulate the hysteresis loop pinched at the origin, with the lobe area varying with the excitation frequency. The direction of the pinched hysteresis loop can be controlled. This graphical modelling method provides an alternative to describe the behaviour of memristors without deriving the coupled non-linear differential equations typically required for physical memristors. The method has been successfully applied to model the Hewlett–Packard memristor device.
Date Issued
2017-01-01
Date Acceptance
2016-09-02
Citation
IET Science Measurement and Technology, 2017, 11 (1), pp.86-96
ISSN
1751-8822
Publisher
Institution of Engineering and Technology
Start Page
86
End Page
96
Journal / Book Title
IET Science Measurement and Technology
Volume
11
Issue
1
Copyright Statement
© 2017 Institution of Engineering and Technology. This paper is a postprint of a paper submitted to and accepted for publication in IET Science Measurement and Technology and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.
Subjects
Applied Physics
0906 Electrical And Electronic Engineering
Publication Status
Published