Reconfigurable Architectures for Cryptographic Systems
Author(s)
Le Masle, Adrien
Type
Thesis
Abstract
Field Programmable Gate Arrays (FPGAs) are suitable platforms for implementing cryptographic
algorithms in hardware due to their flexibility, good performance and low power consumption.
Computer security is becoming increasingly important and security requirements
such as key sizes are quickly evolving. This creates the need for customisable hardware designs
for cryptographic operations capable of covering a large design space. In this thesis we explore
the four design dimensions relevant to cryptography - speed, area, power consumption and
security of the crypto-system - by developing parametric designs for public-key generation and
encryption as well as side-channel attack countermeasures. There are four contributions.
First, we present new architectures for Montgomery multiplication and exponentiation based
on variable pipelining and variable serial replication. Our implementations of these architectures
are compared to the best implementations in the literature and the design space is explored in
terms of speed and area trade-offs.
Second, we generalise our Montgomery multiplier design ideas by developing a parametric
model to allow rapid optimisation of a general class of algorithms containing loops with dependencies
carried from one iteration to the next. By predicting the throughput and the area of
the design, our model facilitates and speeds up design space exploration.
Third, we develop new architectures for primality testing including the first hardware architecture
for the NIST approved Lucas primality test. We explore the area, speed and power
consumption trade-offs by comparing our Lucas architectures on CPU, FPGA and ASIC.
Finally, we tackle the security issue by presenting two novel power attack countermeasures
based on on-chip power monitoring. Our constant power framework uses a closed-loop
control system to keep the power consumption of any FPGA implementation constant. Our
attack detection framework uses a network of ring-oscillators to detect the insertion of a shunt
resistor-based power measurement circuit on a device's power rail. This countermeasure is
lightweight and has a relatively low power overhead compared to existing masking and hiding
countermeasures.
algorithms in hardware due to their flexibility, good performance and low power consumption.
Computer security is becoming increasingly important and security requirements
such as key sizes are quickly evolving. This creates the need for customisable hardware designs
for cryptographic operations capable of covering a large design space. In this thesis we explore
the four design dimensions relevant to cryptography - speed, area, power consumption and
security of the crypto-system - by developing parametric designs for public-key generation and
encryption as well as side-channel attack countermeasures. There are four contributions.
First, we present new architectures for Montgomery multiplication and exponentiation based
on variable pipelining and variable serial replication. Our implementations of these architectures
are compared to the best implementations in the literature and the design space is explored in
terms of speed and area trade-offs.
Second, we generalise our Montgomery multiplier design ideas by developing a parametric
model to allow rapid optimisation of a general class of algorithms containing loops with dependencies
carried from one iteration to the next. By predicting the throughput and the area of
the design, our model facilitates and speeds up design space exploration.
Third, we develop new architectures for primality testing including the first hardware architecture
for the NIST approved Lucas primality test. We explore the area, speed and power
consumption trade-offs by comparing our Lucas architectures on CPU, FPGA and ASIC.
Finally, we tackle the security issue by presenting two novel power attack countermeasures
based on on-chip power monitoring. Our constant power framework uses a closed-loop
control system to keep the power consumption of any FPGA implementation constant. Our
attack detection framework uses a network of ring-oscillators to detect the insertion of a shunt
resistor-based power measurement circuit on a device's power rail. This countermeasure is
lightweight and has a relatively low power overhead compared to existing masking and hiding
countermeasures.
Date Issued
2013-01
Date Awarded
2013-02
Copyright Statement
Attribution NoDerivatives 4.0 International Licence (CC BY-ND)
Advisor
Luk, Wayne
Cadar, Cristian
Sponsor
Engineering and Physical Sciences Research Council ; BlueRISC
Publisher Department
Computing
Publisher Institution
Imperial College London
Qualification Level
Doctoral
Qualification Name
Doctor of Philosophy (PhD)