Slow and steady: measuring and tuning multicore interference
File(s)slow_and_steady_RTAS2020.pdf (401.81 KB)
Accepted version
Author(s)
Iorga, Dan
Sorensen, Tyler
Wickerson, John
Donaldson, Alastair
Type
Conference Paper
Abstract
Now ubiquitous, multicore processors provide repli-cated compute cores that allow independent programs to runin parallel. However, shared resources, such as last-level caches,can cause otherwise-independent programs to interfere with oneanother, leading to significant and unpredictable effects on theirexecution time. Indeed, prior work has shown that speciallycraftedenemy programscan cause software systems of interest toexperience orders-of-magnitude slowdowns when both are run inparallel on a multicore processor. This undermines the suitabilityof these processors for tasks that have real-time constraints.In this work, we explore the design and evaluation of tech-niques for empirically testing interference using enemy programs,with an eye towards reliability (how reproducible the interferenceresults are) and portability (how interference testing can beeffective across chips). We first show that different methodsof measurement yield significantly different magnitudes of, andvariation in, observed interference effects when applied to anenemy process that was shown to be particularly effective inprior work. We propose a method of measurement based onpercentiles and confidence intervals, and show that it providesboth competitive and reproducible observations. The reliability ofour measurements allows us to exploreauto-tuning, where enemyprograms are further specialised per architecture. We evaluatethree different tuning approaches (random search, simulatedannealing, and Bayesian optimisation) on five different multicorechips, spanning x86 and ARM architectures. To show that ourtuned enemy programs generalise to applications, we evaluatethe slowdowns caused by our approach on the AutoBench andCoreMark benchmark suites. Our method achieves a statisticallylarger slowdown compared to prior work in 35 out of 105benchmark/chip combinations, with a maximum difference of3.8×. We envision that empirical approaches, such as ours, willbe valuable for ‘first pass’ evaluations when investigating whichmulticore processors are suitable for real-time tasks.
Date Acceptance
2020-02-16
Publisher
IEEE
Sponsor
Engineering & Physical Science Research Council (E
Grant Number
542716
Source
IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Publication Status
Accepted
Start Date
2020-04-21
Finish Date
2020-04-24
Coverage Spatial
Sydney, Australia