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  5. Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions
 
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Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions
File(s)
fpl21simodense.pdf (282.94 KB)
Accepted version
Author(s)
Papaphilippou, Philippos
Kelly, Paul HJ
Luk, Wayne
Type
Conference Paper
Abstract
Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the design’s memory system is optimised for streaming bandwidth, such as very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications with custom instructions. This paper also provides insights on the effectiveness of adding FPGA resources in general purpose processors in the form of reconfigurable SIMD
instructions.
Date Issued
2021-10-12
Date Acceptance
2021-05-14
Citation
FPL2021. The International Conference on Field-Programmable Logic and Applications (FPL), 2021, pp.391-397
URI
http://hdl.handle.net/10044/1/90081
URL
https://ieeexplore.ieee.org/document/9556386
DOI
https://www.dx.doi.org/10.1109/FPL53798.2021.00082
Publisher
IEEE
Start Page
391
End Page
397
Journal / Book Title
FPL2021. The International Conference on Field-Programmable Logic and Applications (FPL)
Copyright Statement
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Dunnhumby Limited
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Commission of the European Communities
Identifier
https://ieeexplore.ieee.org/document/9556386
Grant Number
PO: 250130012887
516075101 (EP/N031768/1)
EP/P010040/1
671653
Source
FPL2021. The International Conference on Field-Programmable Logic and Applications (FPL)
Subjects
FPGAs
RISC-V
softcore
cache hierarchy
SIMD
custom instructions
streaming
big data
sorting
prefix scan
Publication Status
Published
Start Date
2021-08-30
Finish Date
2021-09-03
Coverage Spatial
Dresden, Germany (virtually)
Date Publish Online
2021-10-12
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