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Efficient arbitration in high-level synthesis from multi-threaded code
Author(s)
Cheng, Jianyi
Type
Dissertation
Version
Imperial Users only
Date Issued
2018
Date Awarded
2018
URI
Creator
Cheng, Jianyi
Description Note
Distinction
Publisher Department
Electrical and Electronic Engineering
Publisher Institution
Imperial College London
Qualification Level
Masters
Qualification Name
MSc
Course Name
Analogue and Digital Integrated Circuit Design