Field-effect transistors using silicon nanowires
prepared by electroless chemical etching
prepared by electroless chemical etching
Author(s)
Zaremba-Tymieniecki, M
Li, Chaunbo
Fobelets, K
Durrani, ZAK
Type
Journal Article
Abstract
Silicon nanowires, prepared by electroless chemical etching, are used to fabricate dual-gate field-effect transistors. The diameters of the nanowires vary from 40–300 nm, with a maximum aspect ratio of ˜3000. Titanium silicide contacts are fabricated on single nanowires. An aluminium top-gate, combined with a back-gate, forms a dual-gate transistor. In an n-channel
device with a nanowire diameter of ˜70 nm, the output characteristics show current saturation, with a maximum current of ˜100 nA. A drain-source threshold voltage exists for current flow,
controlled by the gate voltage, and assists in device turn-off. The ON/OFF current ratio is ˜3000, and the subthreshold swing is ˜780 mV/decade.
device with a nanowire diameter of ˜70 nm, the output characteristics show current saturation, with a maximum current of ˜100 nA. A drain-source threshold voltage exists for current flow,
controlled by the gate voltage, and assists in device turn-off. The ON/OFF current ratio is ˜3000, and the subthreshold swing is ˜780 mV/decade.
Date Issued
2010-08-01
Date Acceptance
2010-05-04
Citation
IEEE Electron Device Letters, 2010, 31, pp.860-862
ISSN
0741-3106
Publisher
Institute of Electrical and Electronics Engineers
Start Page
860
End Page
862
Journal / Book Title
IEEE Electron Device Letters
Volume
31
Copyright Statement
© 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publication Status
Published
Date Publish Online
2010-06-28