This thesis proposes novel optimisations for high performance runtime reconfigurable designs.
For a reconfigurable design,
the proposed approach investigates idle resources introduced by static design approaches,
and exploits runtime reconfiguration to eliminate the inefficient resources.
The approach covers the circuit level, the function level, and the system level.
At the circuit level, a method is proposed for tuning reconfigurable designs with two analytical models:
a resource model for computational and memory resources and memory bandwidth,
and a performance model for estimating execution time.
This method is applied to tuning implementations of finite-difference algorithms,
optimising arithmetic operators and memory bandwidth based on algorithmic parameters,
and eliminating idle resources by runtime reconfiguration.
At the function level, a method is proposed to automatically identify and exploit runtime
reconfiguration opportunities while optimising resource utilisation.
The method is based on Reconfiguration Data Flow Graph,
a new hierarchical graph structure enabling runtime reconfigurable designs to be synthesised in three steps:
function analysis, configuration organisation, and runtime solution generation.
At the system level, a method is proposed for optimising reconfigurable designs by dynamically adapting the designs to available runtime resources in a reconfigurable system. This method includes two steps: compile-time optimisation and runtime scaling, which enable efficient workload distribution, asynchronous communication scheduling, and domain-specific optimisations. It can be used in developing effective servers for high performance applications.