This paper proposes an algorithm for mappinglogical to physical memory resources on Field-ProgrammableGate Arrays (FPGAs). Our greedy strategy based algorithmis specifically designed to facilitate timing closure on modernmulti-die FPGAs for static-dataflow accelerators utilising mostof the on-chip resources. The main objective of the proposedalgorithm is to ensure that specific sub-parts of the design underconsideration can fully reside within a single die to limit inter-die communication. The above is achieved by performing thememory mapping for each sub-part of the design separately whilekeeping allocation of the available physical resources balanced.As a result the number of inter-die connections is reduced onaverage by 50% compared to an algorithm targeting minimalarea usage for real, complex applications using most of the on-chip’s resources. Additionally, our algorithm is the only one outof the four evaluated approaches which successfully producesplace and route results for all 33 applications and benchmarks.