Data Representation Optimisation for Reconfigurable Hardware Design
Author(s)
Osborne, William George
Type
Thesis
Abstract
One of the challenges of designing hardware circuits is representing the data in an
efficient way - minimising area and power while maximising clock frequency. There
are several ways of representing variables, each with different characteristics, such as
the effect arithmetic operations have on the absolute and relative error. In the first
part of this thesis, a new method of transforming arithmetic by combining different
numerical representations to exploit their advantages is discussed. The problem is
formulated as a set of linear equations which are then solved to find the optimal
solution. Algorithms that generate sub-optimal solutions are investigated because
they take a fraction of the time to run. A new reconfigurable device structure is
proposed based on the results presented. In this case, the accuracy of the original
application is guaranteed to be met regardless of the input data.
In many applications, guaranteeing that a transformed design has at least the
same accuracy as the original is not a strong enough constraint. For this reason, the
error on the output is guaranteed to be lower than a specified value. In the second
part of this thesis, accuracy reduction is investigated with the goal of minimising
circuit area. Energy-efficient run-time reconfigurable hardware is automatically
created by systematically deactivating parts of the circuit based on the accuracy
required. A model to determine the conditions under which reconfiguring the chip, if
this is possible, is more energy-efficient than multiplexing is shown. The approach is
expanded to general purpose processors; a new computational model - both software
and hardware architecture - to reduce the energy of future devices is introduced.
efficient way - minimising area and power while maximising clock frequency. There
are several ways of representing variables, each with different characteristics, such as
the effect arithmetic operations have on the absolute and relative error. In the first
part of this thesis, a new method of transforming arithmetic by combining different
numerical representations to exploit their advantages is discussed. The problem is
formulated as a set of linear equations which are then solved to find the optimal
solution. Algorithms that generate sub-optimal solutions are investigated because
they take a fraction of the time to run. A new reconfigurable device structure is
proposed based on the results presented. In this case, the accuracy of the original
application is guaranteed to be met regardless of the input data.
In many applications, guaranteeing that a transformed design has at least the
same accuracy as the original is not a strong enough constraint. For this reason, the
error on the output is guaranteed to be lower than a specified value. In the second
part of this thesis, accuracy reduction is investigated with the goal of minimising
circuit area. Energy-efficient run-time reconfigurable hardware is automatically
created by systematically deactivating parts of the circuit based on the accuracy
required. A model to determine the conditions under which reconfiguring the chip, if
this is possible, is more energy-efficient than multiplexing is shown. The approach is
expanded to general purpose processors; a new computational model - both software
and hardware architecture - to reduce the energy of future devices is introduced.
Date Issued
2011
Date Awarded
2011-11
Copyright Statement
Attribution NoDerivatives 4.0 International Licence (CC BY-ND)
Advisor
Luk, Wayne
Mencer, Oskar
Sponsor
FP6 HARTES and EPSRC
Creator
Osborne, William George
Publisher Department
Computing
Publisher Institution
Imperial College London
Qualification Level
Doctoral
Qualification Name
Doctor of Philosophy (PhD)