Predictive control using an FPGA with application to aircraft control
File(s)
Accepted version
Author(s)
Type
Journal Article
Abstract
Alternative and more efficient computational methods
can extend the applicability of MPC to systems with tight
real-time requirements. This paper presents a “system-on-a-chip”
MPC system, implemented on a field programmable gate array
(FPGA), consisting of a sparse structure-exploiting primal dual
interior point (PDIP) QP solver for MPC reference tracking and
a fast gradient QP solver for steady-state target calculation. A
parallel reduced precision iterative solver is used to accelerate the
solution of the set of linear equations forming the computational
bottleneck of the PDIP algorithm. A numerical study of the effect
of reducing the number of iterations highlights the effectiveness
of the approach. The system is demonstrated with an FPGA-inthe-loop
testbench controlling a nonlinear simulation of a large
airliner. This study considers many more manipulated inputs
than any previous FPGA-based MPC implementation to date,
yet the implementation comfortably fits into a mid-range FPGA,
and the controller compares well in terms of solution quality and
latency to state-of-the-art QP solvers running on a standard PC.
can extend the applicability of MPC to systems with tight
real-time requirements. This paper presents a “system-on-a-chip”
MPC system, implemented on a field programmable gate array
(FPGA), consisting of a sparse structure-exploiting primal dual
interior point (PDIP) QP solver for MPC reference tracking and
a fast gradient QP solver for steady-state target calculation. A
parallel reduced precision iterative solver is used to accelerate the
solution of the set of linear equations forming the computational
bottleneck of the PDIP algorithm. A numerical study of the effect
of reducing the number of iterations highlights the effectiveness
of the approach. The system is demonstrated with an FPGA-inthe-loop
testbench controlling a nonlinear simulation of a large
airliner. This study considers many more manipulated inputs
than any previous FPGA-based MPC implementation to date,
yet the implementation comfortably fits into a mid-range FPGA,
and the controller compares well in terms of solution quality and
latency to state-of-the-art QP solvers running on a standard PC.
Date Issued
2014-05-01
Date Acceptance
2013-06-16
Citation
IEEE Transactions on Control Systems Technology, 2014, 22 (3), pp.1006-1017
ISSN
1558-0865
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Start Page
1006
End Page
1017
Journal / Book Title
IEEE Transactions on Control Systems Technology
Volume
22
Issue
3
Copyright Statement
© 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Grant Number
EP/C512596/1
EP/G031576/1
EP/I012036/1
Subjects
Science & Technology
Technology
Automation & Control Systems
Engineering, Electrical & Electronic
Engineering
Aerospace control
field-programmable gate arrays (FPGAs)
optimization methods
predictive control
INTERIOR-POINT METHODS
IMPLEMENTATION
0102 Applied Mathematics
0906 Electrical and Electronic Engineering
Industrial Engineering & Automation
Publication Status
Published