Reliability has always been an issue in silicon device engineering, but until now it has been
managed by the carefully tuned fabrication process. In the future the underlying physical
limitations of silicon-based electronics, plus the practical challenges of manufacturing with such
complexity at such a small scale, will lead to a crunch point where transistor-level reliability must
be forfeited to continue achieving better productivity.
Field-programmable gate arrays (FPGAs) are built on state-of-the-art silicon processes, but it
has been recognised for some time that their distinctive characteristics put them in a favourable
position over application-specific integrated circuits in the face of the reliability challenge. The
literature shows how a regular structure, interchangeable resources and an ability to reconfigure
can all be exploited to detect, locate, and overcome degradation and keep an FPGA application
running.
To fully exploit these characteristics, a better understanding is needed of the behavioural
changes that are seen in the resources that make up an FPGA under ageing. Modelling is an
attractive approach to this and in this thesis the causes and effects are explored of three important
degradation mechanisms. All are shown to have an adverse affect on FPGA operation, but their
characteristics show novel opportunities for ageing mitigation.
Any modelling exercise is built on assumptions and so an empirical method is developed
for investigating ageing on hardware with an accelerated-life test. Here, experiments show that
timing degradation due to negative-bias temperature instability is the dominant process in the
technology considered.
Building on simulated and experimental results, this work also demonstrates a variety of methods for increasing the lifetime of FPGA lookup tables. The pre-emptive measure of wear-levelling
is investigated in particular detail, and it is shown by experiment how di fferent reconfiguration
algorithms can result in a significant reduction to the rate of degradation.