We propose the first hardware implementation of
standard arithmetic operators – addition, multiplication, and
division – that utilises constant compute resource but allows
numerical precision to be adjusted arbitrarily at run-time.
Traditionally, precision must be set at design-time so that addition
and multiplication, which calculate the least significant digit
(LSD) of their results first, and division, which calculates the
most significant digit (MSD) first, can be chained together. To
get around this, we employ online operators, which are always
MSD-first, and thus allow successive operations to be pipelined.
Even online operators require precision to be fixed at design-time
because multiplication and division traditionally involve parallel
adders. To avoid this, we propose an architecture, which we have
implemented on an FPGA, that reuses a fixed-precision adder and
stores residues in on-chip RAM. As such, we can use a single piece
of hardware to perform calculations to any precision, limited only
by the availability of on-chip RAM. For instance, we obtain an
8x speed-up, compared to the parallel-in-serial-out (PISO) fixedpoint
method, when executing 100 iterations of Newton’s method
at a precision of 64 digits, while the product of circuit area and
latency stays comparable.