Continuing advances in heterogeneous and parallel computing en-
able massive performance gains in domains such as AI and HPC.
Such gains often involve using hardware accelerators, such as FP-
GAs and GPUs, to speed up specific workloads. However, to make
effective use of emerging heterogeneous architectures, optimisa-
tion is typically done manually by highly-skilled developers with
in-depth understanding of the target hardware. The process is te-
dious, error-prone, and must be repeated for each new application.
This paper introduces Design-Flow Patterns, which capture modular,
recurring application-agnostic elements involved in mapping and
optimising application descriptions onto efficient CPU and GPU
targets. Our approach is the first to codify and programmatically
coordinate these elements into fully automated, customisable, and
reusable end-to-end design-flows. We implement key design-flow
patterns using the meta-programming tool Artisan, and evaluate
automated design-flows applied to three sequential C++ applica-
tions. Compared to single-threaded implementations, our approach
generates multi-threaded OpenMP CPU designs achieving up to 18
times speedup on a CPU platform with 32-threads, as well as HIP
GPU designs achieving up to 1184 times speedup on an NVIDIA
GeForce RTX 2080 Ti GPU.