Low latency variational autoencoder on FPGAs
File(s)
Accepted version
Author(s)
Type
Journal Article
Abstract
Variational Autoencoders (VAEs) are at the forefront of generative model research, combining probabilistic theory with neural networks to learn intricate data structures and synthesize complex data. However, designs targeting VAEs are computationally intensive, often involving high latency that precludes real-time operations. This paper introduces a novel low-latency hardware pipeline on FPGAs for fully-stochastic VAE inference. We propose a custom Gaussian sampling layer and a layer-wise tailored pipeline architecture which, for the first time in accelerating VAEs, are optimized through High-Level Synthesis (HLS). Evaluation results show that our VAE design is respectively 82 times and 208 times faster than CPU and GPU implementations. When compared with a state-of-the-art FPGA-based Autoencoder (AE) design for anomaly detection, our VAE design is 61 times faster with the same model accuracy, which shows that our approach contributes to high performance and low latency FPGA-based VAE systems.
Date Issued
2024-06
Date Acceptance
2024-04-01
Citation
IEEE Journal of Emerging and Selected Topics in Circuits and Systems, 2024, 14 (2), pp.323-333
ISSN
2156-3357
Publisher
Institute of Electrical and Electronics Engineers
Start Page
323
End Page
333
Journal / Book Title
IEEE Journal of Emerging and Selected Topics in Circuits and Systems
Volume
14
Issue
2
Copyright Statement
Copyright © 2024 IEEE. This is the author’s accepted manuscript made available under a CC-BY licence in accordance with Imperial’s Research Publications Open Access policy (www.imperial.ac.uk/oa-policy)
License URL
Identifier
http://dx.doi.org/10.1109/jetcas.2024.3389660
Publication Status
Published
Date Publish Online
2024-04-16