Neural networks (NNs) have demonstrated their
potential in a variety of domains ranging from computer
vision to natural language processing. Among various NNs,
two-dimensional (2D) and three-dimensional (3D) convolutional
neural networks (CNNs) have been widely adopted in a broad
spectrum of applications such as image classification and video
recognition, due to their excellent capabilities in extracting 2D
and 3D features. However, standard 2D and 3D CNNs are
not able to capture their model uncertainty which is crucial
for many safety-critical applications including healthcare and
autonomous driving. In contrast, Bayesian convolutional neural
networks (BayesCNNs), as a variant of CNNs, have demonstrated
their ability to express uncertainty in their prediction via a
mathematical grounding. Nevertheless, BayesCNNs have not
been widely used in industrial practice due to their compute
requirements stemming from sampling and subsequent forward
passes through the whole network multiple times. As a result,
these processes significantly increase the amount of computation
and memory consumption in comparison to standard CNNs. This
paper proposes a novel FPGA-based hardware architecture to
accelerate both 2D and 3D BayesCNNs inferred through Monte
Carlo Dropout. Compared with other state-of-the-art accelerators
for BayesCNNs, the proposed design can achieve up to 4 times
higher energy efficiency and 9 times better compute efficiency.
Considering partial Bayesian inference, an automatic framework
is proposed to explore the trade-off between hardware and
algorithmic performance. Extensive experiments are conducted
to demonstrate that our proposed framework can effectively find
the optimal points in the design space.