Repository logo
  • Log In
    Log in via Symplectic to deposit your publication(s).
Repository logo
  • About
  • Communities & Collections
  • Advanced Search
  • Statistics
  • Log In
    Log in via Symplectic to deposit your publication(s).
  1. Home
  2. Faculty of Engineering
  3. Faculty of Engineering
  4. Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs
 
  • Details
Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs
File(s)
MingasITOC15.pdf (536.57 KB)
Accepted version
Author(s)
Mingas, G
Bouganis, C-S
Type
Journal Article
Abstract
Markov Chain Monte Carlo (MCMC) is a method to draw samples from a given probability distribution. Its frequent use for solving probabilistic inference problems, where big-scale data are repeatedly processed, means that MCMC runtimes can be unacceptably large. This paper focuses on population-based MCMC, a popular family of computationally intensive MCMC samplers; we propose novel, highly optimized accelerators in three parallel hardware platforms (multi-core CPUs, GPUs and FPGAs), in order to address the performance limitations of sequential software implementations. For each platform, we jointly exploit the nature of the underlying hardware and the special characteristics of population-based MCMC. We focus particularly on the use of custom arithmetic precision, introducing two novel methods which employ custom precision in the largest part of the algorithm in order to reduce runtime, without causing sampling errors. We apply these methods to all platforms. The FPGA accelerators are up to 114x faster than multi-core CPUs and up to 53x faster than GPUs when doing inference on mixture models.
Date Issued
2015-06-01
Date Acceptance
2015-05-16
Citation
IEEE Transactions on Computers, 2015, 65 (4), pp.1283-1296
URI
http://hdl.handle.net/10044/1/32182
DOI
https://www.dx.doi.org/10.1109/TC.2015.2439256
ISSN
0018-9340
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Start Page
1283
End Page
1296
Journal / Book Title
IEEE Transactions on Computers
Volume
65
Issue
4
Copyright Statement
© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Wellcome Trust
Grant Number
097816/Z/11/A
Subjects
Science & Technology
Technology
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Computer Science
Engineering
Field programmable gate array
graphics processing unit
Markov Chain Monte Carlo
parallel tempering
custom arithmetic precision
PARALLEL
SIMULATIONS
MODELS
Publication Status
Published
About
Spiral Depositing with Spiral Publishing with Spiral Symplectic
Contact us
Open access team Report an issue
Other Services
Scholarly Communications Library Services
logo

Imperial College London

South Kensington Campus

London SW7 2AZ, UK

tel: +44 (0)20 7589 5111

Accessibility Modern slavery statement Cookie Policy

Built with DSpace-CRIS software - Extension maintained and optimized by 4Science

  • Cookie settings
  • Privacy policy
  • End User Agreement
  • Send Feedback