Dynamic deadlock verification for general barrier synchronisation
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Published version
Author(s)
Cogumbreiro, Tiago
Hu, Raymond
Martins, Francisco
Yoshida, N
Type
Journal Article
Abstract
We present Armus, a verification tool for dynamically detecting or avoiding barrier deadlocks. The core designof Armus is based on phasers, a generalisation of barriers that supports split-phase synchronisation, dynamic membership, and optional-waits. This allows Armus to handle the key barrier synchronisation patterns found in modern languages and libraries. We implement Armus for X10 and Java, giving the first sound and complete barrier deadlock verification tools in these settings.
Armus introduces a novel event-based graph model of barrier concurrency constraints that distinguishes task-event and event-task dependencies. Decoupling these two kinds of dependencies facilitates the verification of distributed barriers with dynamic membership, a challenging feature of X10. Our base graph representation can also be dynamically switched between a task-to-task model, Wait-for Graph (WFG), and an event-to-event model, State Graph (SG), to improve the scalability of the analysis. Formally, we show that the verification is sound and complete with respect to the occurrence of deadlock in our core phaser language; and that switching graph representations preserves the soundness and completeness properties. These results are machine checked with the Coq proof assistant. Practically, we evaluate the
runtime overhead of our implementations using three benchmark suites in local and distributed scenarios. Regarding deadlock detection, distributed scenarios show negligible overheads and local scenarios show overheads below1. 15×. Deadlock avoidance is more demanding, and highlights the potential gains from dynamic graph selection. In one benchmark scenario, the runtime overheads vary from: 1.8× for dynamic
selection, 2.6× for SG-static selection, and 5.9× for WFG-static selection.
Armus introduces a novel event-based graph model of barrier concurrency constraints that distinguishes task-event and event-task dependencies. Decoupling these two kinds of dependencies facilitates the verification of distributed barriers with dynamic membership, a challenging feature of X10. Our base graph representation can also be dynamically switched between a task-to-task model, Wait-for Graph (WFG), and an event-to-event model, State Graph (SG), to improve the scalability of the analysis. Formally, we show that the verification is sound and complete with respect to the occurrence of deadlock in our core phaser language; and that switching graph representations preserves the soundness and completeness properties. These results are machine checked with the Coq proof assistant. Practically, we evaluate the
runtime overhead of our implementations using three benchmark suites in local and distributed scenarios. Regarding deadlock detection, distributed scenarios show negligible overheads and local scenarios show overheads below1. 15×. Deadlock avoidance is more demanding, and highlights the potential gains from dynamic graph selection. In one benchmark scenario, the runtime overheads vary from: 1.8× for dynamic
selection, 2.6× for SG-static selection, and 5.9× for WFG-static selection.
Date Issued
2019-03-01
Date Acceptance
2018-05-01
Citation
ACM Transactions on Programming Languages and Systems, 2019, 41 (1), pp.1-38
ISSN
0164-0925
Publisher
Association for Computing Machinery
Start Page
1
End Page
38
Journal / Book Title
ACM Transactions on Programming Languages and Systems
Volume
41
Issue
1
Copyright Statement
© Copyright 2018 held by Owner/Author. This work is licensed under a Creative Commons Attribution International 4.0 License (https://creativecommons.org/licenses/by/4.0/)
Sponsor
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (E
Engineering and Physical Sciences Research Council
Engineering & Physical Science Research Council (EPSRC)
Commission of the European Communities
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Grant Number
ERI 025567 (EP/K034413/1)
PO 20131167
EP/L00058X/1, PO 20131167
EP/K011715/1
612985
EP/N027833/1
20103649
Subjects
Science & Technology
Technology
Computer Science, Software Engineering
Computer Science
Barrier synchronisation
phasers
deadlock detection
deadlock avoidance
X10
Java
SEMANTICS
CLOCKS
TIME
Software Engineering
0803 Computer Software
0806 Information Systems
Publication Status
Published
Article Number
ARTN 1
Date Publish Online
2018-12-11