This paper presents a novel method for fabricating ISFET devices in unmodified CMOS technologies. Conventional CMOS ISFETs utilise the protective passivation coating as the sensing membrane, with the sensed potential being coupled down to the floating MOS gate via a stack of conducting and insulating layers. The proposed structure minimises the use of these layers by exploiting the passivation opening mask, normally intended for bondpad openings. Parasitic effects such as reduced transconductance and trapped charge within the floating gate structure are minimised, resulting in a lower VT and improved chemical transconductance efficiency. Other characteristics including chemical sensitivity, reference leakage current and noise power are at comparable levels with conventional CMOS-based ISFET devices.