Medium voltage direct current (MVDC) networks, as well as other medium voltage power electronic based technologies, have been proposed as a way to increase the penetration of distributed generation. This thesis investigates circuit innovation for multilevel converters at the medium voltage level.

The Neutral Point Clamped AC-Side Cascaded H-Bridge Converter (NPC-AC-CHB), which consists of a three-level NPC-bridge followed by stacks of series connected sub-modules (SMs), has been identified as a promising but under researched converter topology. The NPC-bridge switches slowly to produce a quasi-square wave which delivers the power transfer, while the SM stack switches quickly to improve power quality and enable DC-fault ride-though. Analysis performed shows that, at the optimum modulation index, the SM capacitors can be significantly smaller compared to the established converter topologies, such as the Modular Multilevel Converter (MMC), and thus should provide a much greater power density. A new SM topology for the NPC-AC-CHB, known as a Divisible SM, is proposed. Divisible SMs are shown to provide DC-fault ride-through capability without a significant compromise to efficiency. DC filter design analysis is also performed, and it is shown that passive component sizes can be reduced significantly through the use of an active filter topology. A topology comparison for a medium voltage case study shows that the NPC-AC-CHB, with the improvements proposed in this thesis applied, is both a highly efficient and compact converter topology. Detailed simulation results are shown to validate the analysis and to demonstrate both normal and fault ride-through operation of the NPC-AC-CHB and experimental results for a lab-scale prototype are presented as proof of concept.

This thesis also investigates a new hybrid device SM topology known as the Nested SM. A Nested SM consists of an inner stack of half bridge SMs embedded within an outer full bridge. The inner-stack switches quickly to balance the energy between SM and to perform PWM, while the outer full-bridge switches slowly to insert the inner-SM stack in a positive or negative sense. This topology exploits the various combinations of conduction and switching loss properties of different semiconductor devices to improve overall efficiency. The outer full-bridge is also able to bypass the inner-stack completely to further improve efficiency, this is shown to be able to provide a power loss reduction of up to $43\%$ compared to a reference full-bridge SM case. However, it is shown that under this mode of operation the SM capacitance must be increased to achieve the same voltage ripple. Nested SMs are therefore best suited to applications which prioritise efficiency over power density.