Memristor-based reconfigurable true time delay circuit
Author(s)
Yang, Fan
Serb, Alexander
Wang, Shiwei
Papavassiliou, Christos
Prodromakis, Themistoklis
Type
Journal Article
Abstract
A memristor-controlled CMOS reconfigurable true time delay circuit is introduced in this paper. The delay circuit includesthree stages of g m- C all-pass filter delay elements connected in cascade and memristor-based tunable DC voltage sources. Thememristor value variation changes the DC bias voltage inputs of the delay elements and thus controls the delay time indirectly:The memristor resistance changes in analogue from 10 to 17 kΩ, changing the tunable DC voltage source output from 584- to711-mV DC voltage and the delay from 269 to 632 ps. The delay circuit can work in a frequency range from 50 MHz to 1.6 GHzwith gain ripple smaller than 3 dB. The resolvable delay time step across the delay range is < 8.7 ps, troughing at as low as 0.4 ps.A delay circuit working in the MHz region is also designed to compare the performance with the GHz circuit, and a memristor-programming circuit is built to change the resistance levels of memristors.
Date Issued
2025-08-01
Date Acceptance
2024-11-20
Citation
International Journal of Circuit Theory and Applications, 2025, 53 (8), pp.4935-4947
ISSN
0098-9886
Publisher
Wiley
Start Page
4935
End Page
4947
Journal / Book Title
International Journal of Circuit Theory and Applications
Volume
53
Issue
8
Copyright Statement
© 2024 The Author(s). International Journal of Circuit Theory and Applications published by John Wiley & Sons Ltd. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
License URL
Subjects
ALL-PASS FILTER
analogue
BANDWIDTH
CMOS
COMPACT
DESIGN
DISTRIBUTED MEMS
Engineering
Engineering, Electrical & Electronic
memristor
RECEIVER
RF
RRAM
Science & Technology
Technology
time delay
Publication Status
Published
Date Publish Online
2024-12-05