Design of a four-stage pipelined reduced instruction set computing microprocessor

LI, Jinfeng

doi:https://www.dx.doi.org/10.2139/ssrn.3615850

OA Location

https://doi.org/10.2139/ssrn.3615850

Author(s)

LI, Jinfeng

Type

Working Paper

Abstract

This work presents the design of a reduced instruction set computing (RISC) microprocessor in a four-stage pipeline architecture. The nuts and bolts of each block including timing diagrams are elaborated. To be more specific, a hardware solution to pipeline hazards is proposed and verified, i.e. provided the current result of the arithmetic logic unit (ALU) is employed by the next instruction, the FOWARDING_EN goes high and commands the ALU to select the forwarded result as the updated input, rather than the stale value read from the random-access memory (RAM), thus obviating the need to wait for another two cycles until the expected data has been written back. For the design with data forwarding, two limitations were discovered and tackled successfully by a software solution. Active-HDL was employed to verify the design by simulating a case study, with the code presented in the Appendix.