Global analysis of C concurrency in high-level synthesis
File(s)NadeshTVLSI20.pdf (690.67 KB)
Accepted version
Author(s)
Ramanathan, Nadesh
Constantinides, George
Wickerson, John
Type
Journal Article
Abstract
When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructions, aiming to obtain a schedule that requires as few clock cycles as possible. However, when synthesising multi-threaded C programs, reordering opportunities are limited by the presence ofatomicoperations(‘atomics’), the fundamental concurrency primitivesin C. Existing HLS tools analyse and schedule each thread inisolation. In this article, we argue that thread-local analysisis conservative, especially since HLS compilers have access to the entire program. Hence, we propose a global analysis that exploits information about memory accesses by all threads when scheduling each thread. Implemented in the Leg Up HLS tool, our analysis is sensitive to sequentially-consistent (SC) and weak atomics, and supports loop pipelining. Since the semantics of C atomics is complicated, we formally verify that our analysis correctly implements the C memory model using the Alloy modelchecker. Compared to thread-local analysis, our global analysis achieves a 2.3× average speedup on a set of lock-free datastructures and data-flow patterns. We also apply our analysis to a larger application: a lock-free, streamed, and load-balanced implementation of Google’s PageRank, where we see a 1.3× average speedup compared to thread-local analysis.
Date Issued
2021-01
Date Acceptance
2020-09-07
Citation
IEEE Transactions on Very Large Scale Integration Systems, 2021, 29 (1), pp.24-37
ISSN
1063-8210
Publisher
Institute of Electrical and Electronics Engineers
Start Page
24
End Page
37
Journal / Book Title
IEEE Transactions on Very Large Scale Integration Systems
Volume
29
Issue
1
Copyright Statement
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (EPSRC)
Identifier
https://ieeexplore.ieee.org/document/9234113
Grant Number
EP/P010040/1
Subjects
Computer Hardware & Architecture
0805 Distributed Computing
0906 Electrical and Electronic Engineering
1006 Computer Hardware
Publication Status
Published
Date Publish Online
2020-10-20