An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis
File(s)
Accepted version
Author(s)
Williams, I
Constandinou, TG
Type
Conference Paper
Abstract
This paper presents an energy-efficient neural
stimulator capable of providing charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic
Voltage Scaling (DVS). DC conversion efficiencies of between 63% and 76% are achieved using integrated capacitances of under 1nF and the DVS approach offers power savings of up to 53.5%
compared to the front end of a typical current controlled neural stimulator. Charge balancing is achieved to a low level of accuracy on a single pulse and a much higher accuracy over a series of
pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Monte-Carlo simulations indicate that the charge imbalance will
be less than 0.014% (at 3 sigma ) of charge delivered for a series of pulses. The circuit has been designed in a commercially-available
0.18 m HV CMOS technology and requires a die area
of <0.5 sq. mm for a 16 channel implementation.
stimulator capable of providing charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic
Voltage Scaling (DVS). DC conversion efficiencies of between 63% and 76% are achieved using integrated capacitances of under 1nF and the DVS approach offers power savings of up to 53.5%
compared to the front end of a typical current controlled neural stimulator. Charge balancing is achieved to a low level of accuracy on a single pulse and a much higher accuracy over a series of
pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Monte-Carlo simulations indicate that the charge imbalance will
be less than 0.014% (at 3 sigma ) of charge delivered for a series of pulses. The circuit has been designed in a commercially-available
0.18 m HV CMOS technology and requires a die area
of <0.5 sq. mm for a 16 channel implementation.
Version
Accepted version
Date Issued
2012-08-20
Citation
2012
ISBN
978-1-4673-0218-0
ISSN
0271-4302
Source Title
International Symposium on Circuits and Systems (ISCAS)
Copyright Statement
© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Source
International Symposium on Circuits and Systems (ISCAS)
Source Place
Seoul, Korea
Publication Status
Published
Start Date
2012-05-20
Finish Date
2012-05-23
Coverage Spatial
Seoul, Korea